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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
NO OPERATION Command
For clock stop, CK is held LOW and CK# is held HIGH.
Input Clock Frequency Changes and Clock Stop with CKE HIGH
During CKE HIGH, LPDDR2 devices support input clock frequency changes and clock
stop under the following conditions:
? REFRESH requirements are met
? Any ACTIVATE, READ, WRITE, PRECHARGE, MRW, or MRR commands must have
completed, including any associated data bursts, prior to changing the frequency
? Related timing conditions, t RCD, t WR, t WRA, t RP, t MRW, and t MRR, etc., are met
? CS# must be held HIGH
? Only REFab or REFpb commands can be in process
The device is ready for normal operation after the clock satisfies t CH(abs) and t CL(abs)
for a minimum of 2 × t CK + t XP.
For input clock frequency changes, t CK(MIN) and t CK(MAX) must be met for each clock
cycle.
After the input clock frequency is changed, additional MRW commands may be re-
quired to set the WR, RL, etc. These settings may require adjustment to meet minimum
timing requirements at the target clock frequency.
For clock stop, CK is held LOW and CK# is held HIGH.
NO OPERATION Command
The NO OPERATION (NOP) command prevents the device from registering any unwan-
ted commands issued between operations. A NOP command can only be issued at
clock cycle N when the CKE level is constant for clock cycle N-1 and clock cycle N. The
NOP command has two possible encodings: CS# HIGH at the clock rising edge N; and
CS# LOW with CA0, CA1, CA2 HIGH at the clock rising edge N.
The NOP command will not terminate a previous operation that is still in process, such
as a READ burst or WRITE burst cycle.
Simplified Bus Interface State Diagram
The state diagram (see Figure 81 (page 104)) provides a simplified illustration of the bus
interface, supported state transitions, and the commands that control them. For a com-
plete description of device behavior, use the information provided in the state diagram
with the truth tables and timing specifications.
The truth tables describe device behavior and applicable restrictions when considering
the actual state of all banks.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
103
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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